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AV-51001
2013.12.26
Document Revision History
39
Date
June 2012
February 2012
December 2011
November 2011
August 2011
Arria V Device Overview
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Version
2.0
1.3
1.2
1.1
1.0
Changes
? Restructured the document.
? Added the “ Embedded Memory Capacity ” and “ Embedded Memory
Configurations ” sections.
? Added Table 1, Table 3, Table 12, Table 15, and Table 16.
? Updated Table 2, Table 4, Table 5, Table 6, Table 7, Table 8, Table 9,
Table 10, Table 11, Table 13, Table 14, and Table 19.
? Updated Figure 1, Figure 2, Figure 3, Figure 4, and Figure 8.
? Updated the “ FPGA Configuration and Processor Booting ” and
“ Hardware and Software Development ” sections.
? Text edits throughout the document.
? Updated Table 1 – 7 and Table 1 – 8.
? Updated Figure 1 – 9 and Figure 1 – 10.
? Minor text edits.
Minor text edits.
? Updated Table 1 – 1, Table 1 – 2, Table 1 – 3, Table 1 – 4, Table 1 – 6, Table
1 – 7, Table 1 – 9, and Table 1 – 10.
? Added “ SoC FPGA with HPS ” section.
? Updated “ Clock Networks and PLL Clock Sources ” and “ Ordering
Information ” sections.
? Updated Figure 1 – 5.
? Added Figure 1 – 6.
? Minor text edits.
Initial release.
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